diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index 5c43eca..eb0091b 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -27,12 +27,12 @@
 #include <mpc8xx.h>
 #include <commproc.h>
 
-#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
-    defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+    defined(CONFIG_SYS_SMC_UCODE_PATCH)
 void cpm_load_patch (volatile immap_t * immr);
 #endif
 
@@ -47,7 +47,7 @@
 {
 #ifndef CONFIG_MBX
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
-# ifdef CFG_PLPRCR
+# ifdef CONFIG_SYS_PLPRCR
 	ulong mfmask;
 # endif
 #endif
@@ -55,7 +55,7 @@
 
 	/* SYPCR - contains watchdog control (11-9) */
 
-	immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
+	immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
 
 #if defined(CONFIG_WATCHDOG)
 	reset_8xx_watchdog (immr);
@@ -63,27 +63,27 @@
 
 	/* SIUMCR - contains debug pin configuration (11-6) */
 #ifndef CONFIG_SVM_SC8xx
-	immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
+	immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
 #else
-	immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+	immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
 #endif
 	/* initialize timebase status and control register (11-26) */
 	/* unlock TBSCRK */
 
 	immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
-	immr->im_sit.sit_tbscr = CFG_TBSCR;
+	immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
 
 	/* initialize the PIT (11-31) */
 
 	immr->im_sitk.sitk_piscrk = KAPWR_KEY;
-	immr->im_sit.sit_piscr = CFG_PISCR;
+	immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
 
 	/* System integration timers. Don't change EBDF! (15-27) */
 
 	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
 	reg = immr->im_clkrst.car_sccr;
 	reg &= SCCR_MASK;
-	reg |= CFG_SCCR;
+	reg |= CONFIG_SYS_SCCR;
 	immr->im_clkrst.car_sccr = reg;
 
 	/* PLL (CPU clock) settings (15-30) */
@@ -92,25 +92,25 @@
 
 #ifndef CONFIG_MBX		/* MBX board does things different */
 
-	/* If CFG_PLPRCR (set in the various *_config.h files) tries to
-	 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
-	 * otherwise OR in CFG_PLPRCR so we do not change the current MF
+	/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
+	 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
+	 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
 	 * field value.
 	 *
 	 * For newer (starting MPC866) chips PLPRCR layout is different.
 	 */
-#ifdef CFG_PLPRCR
+#ifdef CONFIG_SYS_PLPRCR
 	if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
 	   mfmask = PLPRCR_MFACT_MSK;
 	else
 	   mfmask = PLPRCR_MF_MSK;
 
-	if ((CFG_PLPRCR & mfmask) != 0)
-	   reg = CFG_PLPRCR;			/* reset control bits   */
+	if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
+	   reg = CONFIG_SYS_PLPRCR;			/* reset control bits   */
 	else {
 	   reg = immr->im_clkrst.car_plprcr;
 	   reg &= mfmask;			/* isolate MF-related fields */
-	   reg |= CFG_PLPRCR;			/* reset control bits   */
+	   reg |= CONFIG_SYS_PLPRCR;			/* reset control bits   */
 	}
 	immr->im_clkrst.car_plprcr = reg;
 #endif
@@ -130,20 +130,20 @@
 	 * when FLASH size has been determined
 	 *
 	 * Depending on the size of the memory region defined by
-	 * CFG_OR0_REMAP some boards (wide address mask) allow to map the
-	 * CFG_MONITOR_BASE, while others (narrower address mask) can't
-	 * map CFG_MONITOR_BASE.
+	 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
+	 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
+	 * map CONFIG_SYS_MONITOR_BASE.
 	 *
-	 * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
-	 * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
+	 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
+	 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
 	 *
 	 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
 	 * base address remains as 0x00000000. However, the address mask
-	 * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
+	 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
 	 * into the Bank0.
 	 *
 	 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
-	 * CFG_BR0_PRELIM in advance.
+	 * CONFIG_SYS_BR0_PRELIM in advance.
 	 *
 	 * [Thanks to Michael Liao for this explanation.
 	 *  I owe him a free beer. - wd]
@@ -165,60 +165,60 @@
     defined(CONFIG_SPC1920)	|| \
     defined(CONFIG_SPD823TS)
 
-	memctl->memc_br0 = CFG_BR0_PRELIM;
+	memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
 #endif
 
-#if defined(CFG_OR0_REMAP)
-	memctl->memc_or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+	memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
 #endif
-#if defined(CFG_OR1_REMAP)
-	memctl->memc_or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+	memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
 #endif
-#if defined(CFG_OR5_REMAP)
-	memctl->memc_or5 = CFG_OR5_REMAP;
+#if defined(CONFIG_SYS_OR5_REMAP)
+	memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
 #endif
 
 	/* now restrict to preliminary range */
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-	memctl->memc_or0 = CFG_OR0_PRELIM;
+	memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
+	memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
 
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 #endif
 
 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
 	memctl->memc_br0 = 0;
 #endif
 
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 #endif
 
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 #endif
 
-#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
-	memctl->memc_or4 = CFG_OR4_PRELIM;
-	memctl->memc_br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 #endif
 
-#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
-	memctl->memc_or5 = CFG_OR5_PRELIM;
-	memctl->memc_br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+	memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
+	memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
 #endif
 
-#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
-	memctl->memc_or6 = CFG_OR6_PRELIM;
-	memctl->memc_br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+	memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
+	memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
 #endif
 
-#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
-	memctl->memc_or7 = CFG_OR7_PRELIM;
-	memctl->memc_br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+	memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
+	memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
 #endif
 
 #endif /* ! CONFIG_MBX */
@@ -249,13 +249,13 @@
 	rpxlite_init ();
 #endif
 
-#ifdef CFG_RCCR			/* must be done before cpm_load_patch() */
+#ifdef CONFIG_SYS_RCCR			/* must be done before cpm_load_patch() */
 	/* write config value */
-	immr->im_cpm.cp_rccr = CFG_RCCR;
+	immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
 #endif
 
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
-    defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+    defined(CONFIG_SYS_SMC_UCODE_PATCH)
 	cpm_load_patch (immr);	/* load mpc8xx  microcode patch */
 #endif
 }
@@ -265,21 +265,21 @@
  */
 int cpu_init_r (void)
 {
-#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
 	bd_t *bd = gd->bd;
 	volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
 #endif
 
-#ifdef CFG_RTCSC
+#ifdef CONFIG_SYS_RTCSC
 	/* Unlock RTSC register */
 	immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
 	/* write config value */
-	immr->im_sit.sit_rtcsc = CFG_RTCSC;
+	immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
 #endif
 
-#ifdef CFG_RMDS
+#ifdef CONFIG_SYS_RMDS
 	/* write config value */
-	immr->im_cpm.cp_rmds = CFG_RMDS;
+	immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;
 #endif
 	return (0);
 }